Sr Principal Verification Engineer (SystemVerilog)

TL;DR

Sr Principal Verification Engineer (SystemVerilog/UVM): Designing and developing UVM-based verification environments for system-level memory IP models with an accent on protocol requirements for SDRAM, UFS, and complex storage. Focus on executing highly complex verification projects, integrating coverage and reporting tools, and optimizing hardware-based verification products.

Location: Shanghai

Company

hirify.global is a leading provider of electronic design automation (EDA) software and hardware tools for the semiconductor industry.

What you will do

• Design, develop, and support UVM-based verification environments and methodologies for system-level memory IP models (SDRAM, UFS, etc.).
• Analyze customer and vendor protocol requirements to execute complex verification projects from requirements through delivery.
• Integrate coverage, reporting, and regression tools to build robust team-level verification structures.
• Research and prototype new tools, languages, and methodologies to enhance product verification and quality.
• Support IP Library regression, OS compliance, process automation, and product release preparations.
• Mentor less experienced engineers and collaborate on cross-functional projects across different geographies.

Requirements

• BS/MS degree in Electrical Engineering (EE) or Computer Science (CS).
• 5-7+ years of professional experience in functional verification.
• Expert understanding of HDLs and HVLs, specifically SystemVerilog and Verilog.
• Deep experience with UVM and C++.
• Solid experience with protocols such as UFS, Unipro, MPHY, SDRAM, Ethernet, PCIe, or USB3/4.
• Very strong English verbal and written skills.

Nice to have

• Experience using hirify.global simulation and/or emulation products.
• Verification experience in memory sub-systems or controller operation.