Staff Engineer (ASIC)

TL;DR

Staff Engineer (ASIC): Developing state-of-the-art IC solutions utilizing CMOS cell-based ASIC technologies with an accent on RTL analysis, synthesis, and physical design. Focus on implementing 5nm/3nm design tape-outs, full chip synthesis, and STA constraint clean-up.

Location: Shanghai, China (Onsite)

Company

hirify.global is a global leader in semiconductor and infrastructure software solutions.

What you will do

• Develop state-of-the-art IC solutions using leading-edge CMOS cell-based ASIC technologies.
• Manage ASIC designs through all development phases, including RTL analysis, synthesis, and design optimization.
• Perform timing verification, simulation, test insertion, and vector generation.
• Execute physical design implementation, including floor planning, placement, and design closure.
• Conduct DRC & LVS checks and provide post-prototype test support.
• Work on cutting-edge 5nm and 3nm design tape-outs.

Requirements

• Solid VLSI background and deep understanding of the ASIC design flow.
• Proven experience with tape-outs in 5nm and below process designs.
• Ability to independently handle block implementation and top-level tasks.
• Strong problem-solving and communication skills.
• Master's degree in Microelectronics or a related discipline.

Nice to have

• Experience with DFT insertion and Power/IVD analysis.
• Expertise in DRC/LVS, Top Floorplan, STA, and Low Power design.
• Proficiency in scripting languages such as Perl, Tcl, or Python.