Principal Engineer (Design Technology Co-optimization)

TL;DR

Principal Engineer (Design Technology Co-optimization): Driving the optimization of standard cell libraries on leading-edge process nodes to meet internal and external foundry customer needs with an accent on design-technology co-optimization (DTCO) and foundational IP development. Focus on collaborating with physical design engineers and EDA partners to maximize power, performance, and area (PPA) entitlement while minimizing process risks.

Location: Must be based in Hillsboro, Oregon (Hybrid)

Salary: $220,920–$311,890 USD

Company

hirify.global is a global leader in semiconductor manufacturing, delivering cutting-edge silicon process and packaging technology for the AI era.

What you will do

• Lead the optimization of standard cell libraries on leading-edge process nodes.
• Interface with key foundry customers to identify technology and library gaps.
• Collaborate with physical design engineers to tune layouts for improved PPA.
• Partner with EDA vendors to optimize cell content and improve technology entitlement.
• Drive co-optimization efforts across hirify.global foundry technology development teams.

Requirements

• Ph.D. or Master's degree in Electrical Engineering or Computer Science.
• 10+ years of industry experience in semiconductor technology.
• Strong understanding of foundation IP design and DTCO.
• Expertise in standard cell library design, MOSFET characteristics, and local layout effects.
• Proficiency in library cell characterization methodology and Spice circuit simulations.
• Must be eligible to work in the United States.

Nice to have

• Experience in product design with signoff methodology knowledge.
• Familiarity with pre and post-Si foundry benchmarking practices.
• Experience in foundation IP Si validation.

Culture & Benefits

• Competitive total compensation package including stock bonuses.
• Comprehensive health, retirement, and vacation programs.
• Hybrid work model allowing flexibility between on-site and off-site work.
• Opportunity to work on state-of-the-art semiconductor manufacturing technology.