SoC Compute/Memory Subsystem Architect

Location: Hybrid, Ireland, Leixlip; employees split their time between the hirify.global site and off-site work.

Annual salary: €75,200–€139,700, plus potential additional compensation and benefits.

Company

hirify.global develops semiconductor and computing technologies, including networking silicon, IPU/DPU platforms, and solutions for hyperscale data centers, cloud infrastructure, and AI workloads.

What you will do

• Define CPU clusters, multi-level cache hierarchies, coherency models, and compute subsystem architecture.
• Architect DDR/LPDDR memory interfaces, controllers, scheduling policies, bandwidth provisioning, and scaling strategies.
• Design SMMU/IOMMU capabilities for virtualization-heavy IPU workloads, including tenant isolation and shared or isolated memory models.
• Integrate compute, networking, storage, accelerator, and SoC fabric subsystems while minimizing data copies, latency, and bandwidth overhead.
• Define power-efficiency, DVFS, bandwidth throttling, prioritization, and per-subsystem scaling strategies.
• Lead multi-generation architecture roadmaps and align decisions across networking, firmware, operating system, drivers, validation, and performance modeling teams.

Requirements

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related STEM field.
• 10+ years of experience in SoC, CPU, or memory subsystem architecture.
• Experience with CPU architecture, cache hierarchies, DDR/HBM memory subsystems, controllers, and QoS.
• Experience with coherent and non-coherent interconnect architectures and system-level performance and PPA trade-off analysis.
• Ability to drive architecture definition from concept through silicon.
• Experienced-hire level with strong cross-functional leadership and systems-thinking skills.

Nice to have

• Postgraduate degree in Electrical Engineering, Computer Engineering, or a related STEM field.
• ARM and x86 compute and memory subsystem experience, including NUMA systems and cache coherency.
• Experience with IPU, SmartNIC, or accelerator-centric SoCs in cloud and hyperscale environments.
• Familiarity with PCIe, CXL, and high-performance I/O memory semantics.
• Multi-generation architectural ownership and experience mentoring other architects.

Culture & Benefits

• Hybrid work model combining on-site and off-site work.
• Competitive total compensation package.
• Benefits package for employees and their families.
• Opportunity to collaborate across networking, firmware, operating system, driver, validation, and performance teams.