Experienced ASIC Verification Engineer (ASIC)

TL;DR

Experienced ASIC Verification Engineer (ASIC/UVM): Performing pre-silicon verification of in-house hardware IPs and subsystems for the ARTPEC SoC with an accent on coverage-driven constrained random verification. Focus on debugging complex hardware designs, implementing verification software tools in Python, and exploring new verification methodologies.

Location: Lund, Sweden (Onsite)

Company

hirify.global is a global network technology leader specializing in innovative solutions for video surveillance, access control, and audio systems.

What you will do

• Execute pre-silicon verification of in-house developed hardware IPs and subsystems using simulation and formal methods.
• Implement and maintain efficient software tools essential for the verification process, primarily using Python.
• Debug and identify potential issues within complex hardware designs.
• Evaluate and investigate new verification technologies and tools to improve the hardware flow.
• Collaborate within an agile team to ensure the correctness of the 10th generation ARTPEC SoC.

Requirements

• At least 3 years of professional experience in ASIC verification.
• Strong expertise in Coverage-driven Constrained Random Verification.
• Proficiency in SystemVerilog and UVM at the module and/or sub-system levels.
• Keen interest and experience in programming, specifically with Python.
• Must be based in or able to work from Lund, Sweden.

Nice to have

• Experience with formal verification, including connectivity checking and formal property verification.
• Programming proficiency in C, C++, or SystemC.
• Knowledge of Transaction Level Modeling (TLM).

Culture & Benefits

• Creative and collaborative environment that encourages knowledge sharing.
• Focus on continuous growth of expertise and individual responsibilities.
• Opportunities to write technical papers and present at international conferences.
• Inclusive and diverse corporate culture with a commitment to sustainability.