IP Design Verification Engineer (UCIe)

TL;DR

IP Design Verification Engineer (UVM/SystemVerilog): Developing and optimizing verification environments for UCIe Mixed-Signal IP for Server SoCs with an accent on constrained-random test generation and RTL debug. Focus on building UVM test benches, performing gate-level functional verification, and implementing SVA to ensure high-quality silicon delivery.

Location: Hybrid; must be based in the US (Santa Clara, CA or Hillsboro, OR)

Salary: $141,910–$200,340 USD

Company

hirify.global is a global leader in the design and manufacture of silicon products that empower technology worldwide.

What you will do

• Develop test benches and directed/constrained random tests using UVM.
• Collaborate with design teams to review specifications, architecture, and define verification plans.
• Execute RTL and gate-level functional verification, debug failures, and analyze coverage.
• Support mixed-signal verification utilizing Verilog models of analog IP.

Requirements

• Bachelor's degree in EE/CS with 5+ years experience, Master's with 3+ years, or PhD with 2+ years.
• Proven experience in IP or SoC verification using System Verilog and UVM.
• Ability to interpret technical specifications and RTL code for debugging.
• Experience implementing verification environments with constrained-random stimulus.
• Proficiency in code/functional coverage analysis and writing System Verilog Assertions (SVA).
• Must be based in the US (Santa Clara, CA or Hillsboro, OR) for hybrid work.

Nice to have

• Experience with Mixed-Signal Verification.
• Knowledge of UCIe, PCIe, or I/O protocols.

Culture & Benefits

• Competitive total compensation package including stock bonuses.
• Comprehensive health, retirement, and vacation benefit programs.
• Hybrid work model allowing a split between on-site and off-site work.
• Fast-paced environment focused on continuous learning and professional growth.