Lead Design Engineer - Verification (VLSI)

TL;DR

Lead Design Engineer - Verification (VLSI): Developing and executing verification plans for SOC and IP blocks with an accent on RTL verification and test coverage. Focus on bridging communication between local and global teams while optimizing verification strategies for high-performance protocols.

Location: Shanghai, China

Company

hirify.global is a leading provider of electronic design automation (EDA) software and hardware tools.

What you will do

• Develop and execute verification plans for SOC and IP blocks to ensure design intent and testability.
• Perform RTL verification using industry-standard methodologies such as UVM and SystemVerilog.
• Collaborate with design engineers to resolve complex debug issues and optimize verification strategies.
• Provide high-quality support and service to customer and internal engineering teams.
• Conduct coverage analysis and regression testing to achieve verification goals.
• Enhance verification environments and develop reusable testbenches.

Requirements

• Bachelor’s or Master’s degree in Electrical/Computer Engineering or a related field.
• 3–5 years of experience in VLSI/SOC design verification.
• Strong expertise in SystemVerilog, UVM, and industry-standard verification tools.
• Hands-on experience with protocols such as AMBA, PCIe, USB, MIPI, or DDR/LPDDR.
• Experience with ARM/RISC-V Processor integration is preferred.