Digital Verification Engineer (Security)

TL;DR

Digital Verification Engineer (Security): Developing and verifying complex security hardware architectures and co-processors for automotive and mobile applications with an accent on UVM-based testbench development and constrained random verification. Focus on achieving coverage closure, refining verification strategies, and ensuring the reliability of high-end security IP.

Location: Glasgow, UK (Onsite)

Company

hirify.global is a global leader in secure connectivity solutions for embedded applications, serving markets including automotive, industrial, and mobile.

What you will do

• Verify digital hardware architectures for security features and co-processors.
• Create, review, and maintain comprehensive verification plans.
• Develop verification strategies, testbenches, and environments using advanced methodologies.
• Track verification progress and ensure metrics-driven quality standards.
• Collaborate on introducing emerging verification methodologies into existing flows.
• Perform debugging across complex simulation environments to ensure design integrity.

Requirements

• BSc or MSc degree in Electronics or Electrical Engineering.
• Strong hands-on experience with SystemVerilog for testbench development.
• Proven expertise in UVM, including component creation, sequences, and monitors.
• Solid understanding and practical use of Constrained Random Verification.
• Experience with Metrics-Driven Verification and functional coverage.
• Ability to write SystemVerilog Assertions (SVA) for protocol checking.
• Demonstrated success in achieving Coverage Closure.

Nice to have

• Knowledge of Formal Verification methods.