Manufacturing Test Engineer (AI)

TL;DR

Manufacturing Test Engineer (AI Hardware): Driving manufacturing test strategy and execution for AI-native silicon and system-level hardware with an accent on test coverage across the product lifecycle, including ICT and FCT. Focus on scaling production-ready test solutions, improving yield, and collaborating with external system integrators to ensure manufacturing readiness.

Location: San Francisco, CA

Salary: $207K – $365K + Equity

Company

hirify.global is an AI research and deployment company dedicated to ensuring that general-purpose artificial intelligence benefits all of humanity.

What you will do

• Define and drive manufacturing test strategies for boards, trays, and system-level hardware assemblies across EVT, DVT, PVT, and production ramp.
• Develop and manage test coverage for ICT, board-level functional tests (FCT), tray-level integration, and system-level bring-up.
• Partner with electrical, system, and software teams to define requirements, validate failure isolation, and review test scripts.
• Collaborate with JDMs, contract manufacturers, and equipment vendors to implement and qualify test stations and production workflows.
• Analyze manufacturing test results, yield trends, and failure paretos to identify gaps and drive corrective actions.
• Lead the debug of manufacturing test failures, determining root causes across design, process, fixture, or software.

Requirements

• Bachelor’s degree in Electrical, Computer, or Manufacturing Engineering, or equivalent practical experience.
• 5+ years of experience in manufacturing test engineering, product test, or NPI test development.
• Experience with ICT, board-level functional tests, and system-level manufacturing for servers or AI Accelerators.
• Proven experience working with contract manufacturers, JDMs, or system integrators.
• Must be based in San Francisco.
• Candidates may need to meet legal status requirements to comply with U.S. export control laws.

Nice to have

• Experience with Python/Bash scripting, Linux-based diagnostics, and CI/release controls in factory environments.
• Knowledge of DFT (Design for Test) principles and their influence on production yield.
• Experience supporting high-volume production ramps in Asia or other global manufacturing hubs.
• Experience with failure analysis and root-cause investigation processes.

Culture & Benefits

• Opportunity to work on the next generation of AI-native silicon for supercomputing infrastructure.
• Fast-moving, high-ownership environment with high expectations for execution.
• Competitive compensation package including equity.
• Commitment to an inclusive, equal-opportunity work environment.