Debug Architect (AI)

TL;DR

Debug Architect (AI/Hardware): Defining and scaling debug and trace capabilities for next-generation CPU and AI silicon with an accent on hardware-software boundaries and post-silicon environments. Focus on designing scalable debug architectures, validating trace features, and establishing robust post-silicon debug infrastructure.

Location: Hybrid, based out of Toronto, Canada

Company

hirify.global is building next-generation CPU and AI silicon to revolutionize AI performance, ease of use, and cost efficiency.

What you will do

• Define and implement scalable debug architecture across multiple CPU and AI product lines.
• Design and validate hardware debug and trace features during development and verification.
• Prove debug capabilities during silicon development and ensure production readiness.
• Support silicon bring-up and establish robust post-silicon debug infrastructure.
• Collaborate with hardware, software, and deployment teams to enable efficient debugging and performance analysis.

Requirements

• Experience in hardware debug for CPU, SoC, or ASIC systems, including bring-up and post-silicon environments.
• Strong understanding of processor architecture (RISC-V, x86, or ARM).
• Familiarity with debug, profiling, and trace methodologies, including industry standards like iJTAG.
• Experience working across hardware and software boundaries, including firmware and driver interaction.
• Proficiency in HDL (Verilog or VHDL) and programming tools including Python and Git.
• Must be eligible to access U.S. export-controlled technology (EAR compliance).

Culture & Benefits

• Highly competitive compensation package and benefits.
• Collaborative environment with a focus on curiosity and solving hard problems.
• Opportunity to contribute to cutting-edge AI technology and high-performance RISC-V CPUs.
• Equal opportunity employer.