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Senior Engineer, CPU RTL Design (AI)

Формат работы
hybrid
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

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TL;DR
Senior Engineer, CPU RTL Design (AI) (RISC-V/RTL): Defining and implementing RTL and microarchitecture for high-performance RISC-V CPUs with an accent on functional, timing, and power convergence. Focus on optimizing power, performance, and area, debugging across pre-silicon and post-silicon environments, and collaborating on complex CPU design challenges.

Location: Hybrid role based in Austin, Texas, or Santa Clara, California, United States

Compensation: $100,000–$500,000, including base and variable compensation targets

Company

Tenstorrent develops AI computing technology and high-performance RISC-V CPUs as part of an integrated AI platform spanning software, compilers, platforms, networking, and semiconductors.

What you will do

  • Define CPU microarchitecture and own RTL design for part of a high-performance RISC-V CPU block.
  • Implement and optimize RTL using Verilog or VHDL.
  • Collaborate with design verification, physical design, performance, validation, and test teams to meet functional, timing, and power goals.
  • Run RTL experiments and evaluate power, performance, and area trade-offs.
  • Debug RTL and logic across multiple design hierarchies and pre-silicon and post-silicon environments.
  • Improve RTL design tools, flows, and development methodologies.

Requirements

  • Experience with CPU microarchitecture, including areas such as rename, scheduler, reorder buffer, load/store, branch prediction, cache, or datapath design.
  • Strong RTL coding skills with Verilog or VHDL.
  • Familiarity with industry-standard simulation, synthesis, and power-analysis tools.
  • Experience debugging RTL and logic across multiple design hierarchies and pre-silicon and post-silicon environments.
  • Experience defining microarchitecture, writing design specifications, and analyzing performance-driven trade-offs.
  • Ability to work in a hybrid setup based in Austin, Texas, or Santa Clara, California. Access to U.S. export-controlled technology may be subject to U.S. export laws and eligibility requirements.

Culture & Benefits

  • Work in a deeply technical and collaborative CPU design team.
  • Gain end-to-end exposure to CPU design from microarchitecture through timing and power convergence.
  • Work on both pre-silicon and post-silicon optimization of high-performance CPU designs.
  • Integrate open-source and industry-standard tools into RTL development flows.
  • Receive a competitive compensation package and benefits.

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