Senior CPU RTL Design Engineer (RISC-V)

TL;DR

Senior CPU RTL Design Engineer (RISC-V): Developing and implementing RTL for high-performance RISC-V CPUs with an accent on microarchitecture definition, power-performance-area optimization, and timing convergence. Focus on collaborating with DV and PD teams to deliver robust designs for cutting-edge AI hardware platforms.

Location: Must be based in or able to work from Austin, TX or Santa Clara, CA (Hybrid)

Salary: $100,000–$500,000

Company

hirify.global is a leading AI hardware company building high-performance RISC-V CPUs and AI platforms to revolutionize computing efficiency.

What you will do

• Own RTL design and microarchitecture development for high-performance RISC-V CPU blocks.
• Collaborate with DV, PD, and performance teams to meet functional, timing, and power goals.
• Optimize power, performance, and area through innovative RTL experiments and analysis.
• Partner with validation and test teams to ensure robust pre-silicon and post-silicon execution.
• Enhance RTL design environments, tools, and methodologies to improve development efficiency.

Requirements

• Must be eligible to access U.S. export-controlled technology (U.S. citizenship or permanent residency may be required).
• Expertise in CPU microarchitecture (Rename, Scheduler, ROB, Load Store, Branch Prediction, Cache, or Datapath).
• Proficiency in RTL coding (Verilog/VHDL) and industry-standard simulation/synthesis tools.
• Experience in debugging RTL/logic across multiple design hierarchies.
• Background in microarchitecture definition and performance-driven trade-off analysis.

Culture & Benefits

• Competitive compensation package including base and variable targets.
• Opportunity to work on end-to-end CPU design from microarchitecture to silicon.
• Collaborative environment focused on solving complex, cutting-edge technical challenges.
• Equal opportunity employer committed to innovation and curiosity.