Photolithography Process Engineer (Semiconductor)

TL;DR

Photolithography Process Engineer (Semiconductor): Managing and optimizing the photolithography process in a high-volume semiconductor wafer manufacturing environment with an accent on cost reduction and process stability. Focus on implementing Six-Sigma statistical methodologies, reducing wafer scrap, and optimizing tool utilization and availability.

Location: Onsite in Chandler, USA

Company

hirify.global is a world leader in secure connectivity solutions for embedded applications, serving the automotive, industrial & IoT, mobile, and communication infrastructure markets.

What you will do

• Reduce overall costs of non-conformal waste, specifically wafer scrap and photo rework.
• Implement process SPC and perform optimization utilizing Six-Sigma statistical methodology.
• Develop and write standard work procedure documents for Out of Control Action Plans (OCAP).
• Improve tool utilization and availability in collaboration with manufacturing and industrial engineering for capacity planning.
• Source and release new equipment into the production process.
• Train process technicians and FAB associates on tool operation and wafer dispositioning.

Requirements

• Must be based in or able to work onsite in Chandler
• BS or MS degree in engineering or a relevant field of studies.
• More than 5 years of process engineering experience in a high-volume semiconductor manufacturing environment.
• Experience with Six-Sigma statistical methodology.

Nice to have

• Previous experience with ASML Scanner, Canon Stepper, TEL ACT 8 or Mark 7 track, KLA 8100 CDSEM or Archers.

Culture & Benefits

• Access to online and offline learning opportunities for professional skill development.
• Inclusive work environment with a strong commitment to diversity, equality, and sustainability.
• Employment at a leading NASDAQ-listed global technology corporation.