Staff Engineer, Digital IC Design (ASIC)

TL;DR

Staff Engineer, Digital IC Design (ASIC/DSP): Designing, verifying, and evaluating digital circuits for high-speed data communication ICs with an accent on PAM4 optical DSPs and PHY transceivers. Focus on developing micro-architectures, optimizing DSP algorithms, and performing PPA analysis to support AI and cloud data center networks.

Location: Ho Chi Minh, Vietnam

Company

hirify.global provides essential semiconductor solutions for data infrastructure across enterprise, cloud, and AI architectures.

What you will do

• Design RTL for PHY transceivers with data rates from 25Gbps to 224Gbps.
• Develop ASIC specifications and micro-architecture for digital signal processing and communications algorithms.
• Analyze DSP challenges and optimize performance vs. cost (power, area, complexity) trade-offs.
• Perform functional verification, RTL lint, cross clock domain (CDC) analysis, and static timing analysis.
• Execute post-silicon debug and correlation.

Requirements

• Experience with high-speed DSP, FEC (Forward Error Correction), PCIe, and UCIe.
• Proficiency in Verilog, SystemVerilog, Matlab, Perl, and Unix Shell.
• Proven experience in VLSI design from micro-architecture specification to timing closure.
• Bachelor's degree with 3-5 years of experience, or Master's/PhD with 2-3 years of experience in Electrical Engineering or Computer Science.
• Must be eligible to access export-controlled information under U.S. export control laws (EAR).

Culture & Benefits

• Competitive compensation and comprehensive benefits package.
• Collaborative, transparent, and inclusive work environment.
• Access to tools and resources for professional growth and development.