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1 дСнь назад

SOC Top Level Physical Design Engineer (AI)

159Β 200 - 247Β 600$
Π’ΠΈΠΏ Ρ€Π°Π±ΠΎΡ‚Ρ‹
fulltime
Π“Ρ€Π΅ΠΉΠ΄
senior
Английский
b2
Π‘Ρ‚Ρ€Π°Π½Π°
US
Вакансия ΠΈΠ· списка Hirify.GlobalВакансия ΠΈΠ· Hirify Global, списка ΠΌΠ΅ΠΆΠ΄ΡƒΠ½Π°Ρ€ΠΎΠ΄Π½Ρ‹Ρ… tech-ΠΊΠΎΠΌΠΏΠ°Π½ΠΈΠΉ
Для мэтча ΠΈ ΠΎΡ‚ΠΊΠ»ΠΈΠΊΠ° Π½ΡƒΠΆΠ΅Π½ Plus

ΠœΡΡ‚Ρ‡ & Π‘ΠΎΠΏΡ€ΠΎΠ²ΠΎΠ΄

Для мэтча с этой вакансиСй Π½ΡƒΠΆΠ΅Π½ Plus

ОписаниС вакансии

ВСкст:
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TL;DR

SOC Top Level Physical Design Engineer (AI): Designing and optimizing custom silicon for AWS Machine Learning servers with an accent on full chip floorplan, placement, and physical verification. Focus on driving PV signoff, executing next-generation integration methodologies, and ensuring high design quality for advanced technology nodes.

Location: Must be based in Austin, TX or Cupertino, CA

Salary: $159,200 – $247,600

Company

Annapurna Labs, an hirify.global company, designs custom silicon and software stacks to accelerate cloud-scale machine learning innovation.

What you will do

  • Drive full chip floorplan, placement, integration, PV signoff, and tapeout.
  • Collaborate with front-end teams to align RTL with physical design requirements early in the design cycle.
  • Define and optimize next-generation physical verification and integration methodologies using FC, Calibre, and IC Validator.
  • Perform DRC, LVS, and PERC verifications.
  • Interface with foundries for rule deck updates and violation waivers.
  • Mentor junior engineers on physical verification methodologies and closure.

Requirements

  • Must be based in or be able to work from Austin, TX or Cupertino, CA.
  • BS + 10 years or MS + 7 years in EE/CS or a related field.
  • 5+ years of experience in physical verification for advanced technology nodes.
  • Expert knowledge of industry-standard physical verification tools (Calibre, IC Validator, PVS).
  • Proven track record of successful tape-outs.
  • Proficiency in scripting with Python, Perl, Bash, or PowerShell.

Nice to have

  • Experience with integration and verification in nodes 5nm or below.
  • Expertise in DFM (Design for Manufacturing) and reliability verification (ESD, EM, IR drop).
  • Knowledge of custom and digital design flows.
  • Experience solving physical design challenges for DDR, PCIe, and fabrics.

Culture & Benefits

  • Competitive compensation including sign-on payments and Restricted Stock Units (RSUs).
  • Comprehensive health insurance (medical, dental, vision, prescription).
  • 401(k) matching and paid time off.
  • Parental leave and mental health support.
  • Inclusive culture with support for workplace accommodations.

Π‘ΡƒΠ΄ΡŒΡ‚Π΅ остороТны: Ссли Ρ€Π°Π±ΠΎΡ‚ΠΎΠ΄Π°Ρ‚Π΅Π»ΡŒ просит Π²ΠΎΠΉΡ‚ΠΈ Π² ΠΈΡ… систСму, ΠΈΡΠΏΠΎΠ»ΡŒΠ·ΡƒΡ iCloud/Google, ΠΏΡ€ΠΈΡΠ»Π°Ρ‚ΡŒ ΠΊΠΎΠ΄/ΠΏΠ°Ρ€ΠΎΠ»ΡŒ, Π·Π°ΠΏΡƒΡΡ‚ΠΈΡ‚ΡŒ ΠΊΠΎΠ΄/ПО, Π½Π΅ Π΄Π΅Π»Π°ΠΉΡ‚Π΅ этого - это мошСнники. ΠžΠ±ΡΠ·Π°Ρ‚Π΅Π»ΡŒΠ½ΠΎ ΠΆΠΌΠΈΡ‚Π΅ "ΠŸΠΎΠΆΠ°Π»ΠΎΠ²Π°Ρ‚ΡŒΡΡ" ΠΈΠ»ΠΈ ΠΏΠΈΡˆΠΈΡ‚Π΅ Π² ΠΏΠΎΠ΄Π΄Π΅Ρ€ΠΆΠΊΡƒ. ΠŸΠΎΠ΄Ρ€ΠΎΠ±Π½Π΅Π΅ Π² Π³Π°ΠΉΠ΄Π΅ β†’