Назад
Company hidden
10 часов назад

Principal ASIC Synthesis and Timing Engineer (ASIC)

190 000 - 280 000$
Формат работы
remote (только USA)
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
Для мэтча и отклика нужен Plus

Мэтч & Сопровод

Для мэтча с этой вакансией нужен Plus

Описание вакансии

Текст:
/

TL;DR

Principal ASIC Synthesis and Timing Engineer (ASIC): Leading the implementation of complex SoCs for next-generation satellite and space systems with an accent on RTL-to-synthesis flow, PPA optimization, and timing closure. Focus on driving design convergence, managing external physical design partners, and ensuring first-pass silicon success in advanced FinFET technologies.

Location: Remote (Must be a U.S. Person per ITAR regulations)

Salary: $190,000 – $280,000 + equity

Company

hirify.global is a Series C startup building high-power satellite platforms designed for missions from LEO to deep space.

What you will do

  • Own the complete RTL-to-Synthesis flow at both block and top levels.
  • Optimize performance, power, and area (PPA) through design methodologies and automation scripts.
  • Drive timing closure across multiple voltage and process corners, including sign-off with foundry-qualified tools.
  • Manage and technically guide external physical design partners and service vendors to ensure quality standards.
  • Develop end-to-end formal verification methodologies and handle Lint, CDC, and UPF checks.
  • Collaborate with post-silicon and test teams to support chip bring-up and debug.

Requirements

  • B.S. or M.S. in Electrical Engineering, Computer Engineering, or a related field.
  • 10+ years of experience in ASIC design for high-performance SoCs.
  • Proven expertise in RTL-to-GDSII flows using industry tools (Synopsys, Cadence, or Siemens).
  • Hands-on experience with timing closure, IR drop analysis, and low power/ECO implementation.
  • Deep understanding of physical design constraints for multi-clock and multi-voltage hierarchical SoCs.
  • Must be a U.S. Person (citizen, lawful permanent resident, etc.) as defined by ITAR regulations.

Nice to have

  • Exposure to radiation-hardened or space-qualified ASICs.
  • Experience driving tapeouts through TSMC.
  • Familiarity with Gate-All-Around (GAA) technologies.

Culture & Benefits

  • Comprehensive medical, dental, and vision coverage.
  • Equity ownership in the company.
  • Paid time off and paid parental leave.
  • Opportunity to work on groundbreaking space technology in a fast-paced startup environment.

Будьте осторожны: если работодатель просит войти в их систему, используя iCloud/Google, прислать код/пароль, запустить код/ПО, не делайте этого - это мошенники. Обязательно жмите "Пожаловаться" или пишите в поддержку. Подробнее в гайде →