Senior Digital Verification Engineer (DAC/ADC DSP Correction)

TL;DR

Senior Digital Verification Engineer (DAC/ADC DSP Correction): Implementing verification strategies for Wavelogic modem functional blocks and subsystems with an accent on simulation, formal, and coverage-driven methods. Focus on developing SystemVerilog UVM testbenches, validating architectural blocks, and debugging failures in DAC/ADC DSP correction components.

Location: Onsite in Ottawa, Canada or Braunschweig, Germany

Salary: $109,000 - $174,000 CAD (Ottawa)

Company

Global leader in high-speed connectivity developing the Wavelogic family of modem products.

What you will do

• Read and understand architecture and functional requirements specifications, collaborating with systems engineers and architects.
• Validate architectural functional blocks using simulation, formal, and coverage methods.
• Develop verification test plans, functional coverage, and formal verification plans.
• Create testbench environments, components, agents, scoreboards, and test scenarios using SystemVerilog UVM and/or C.
• Perform coverage-driven verification, monitor regressions, and debug failures with designer support.
• Provide regular status updates on verification progress.

Requirements

• 5+ years of relevant industry experience
• Bachelor's degree in Electrical or Computer Engineering
• Significant experience with SystemVerilog, UVM, SVA, and major simulators
• Proven ability to develop comprehensive digital verification and coverage strategies

Nice to have

• Experience with formal verification methods
• Familiarity with Python, Make, bash, OOP, C, C++
• Proficiency in Jira for bug tracking and GIT for source code management
• Knowledge of digital analog converters (DAC/ADC) and PLLs

Culture & Benefits

• Flexible work environment prioritizing growth, well-being, and belonging
• Comprehensive benefits including medical, dental, vision plans
• Participation in 401(K) (USA) & DCPP (Canada) with company matching, ESPP, EAP
• Company-paid holidays, paid sick leave, vacation time, Paid Family Leave compliance