Principal Design Engineer (SOC Verification)

TL;DR

Principal Design Engineer (SOC Verification): Developing and architecting scalable SV-UVM based verification environments for subsystem and SOC level designs with an accent on ARM-based architectures and AMBA protocols. Focus on defining verification strategies, executing complex test cases to achieve coverage goals, and mentoring junior engineers to ensure high-quality Si realization.

Location: Austin, TX, USA

Company

A leading company providing electronic design automation (EDA) software and hardware tools for chip design.

What you will do

• Architect and develop scalable SV-UVM verification environments from scratch for complex modules and SOCs.
• Define verification architecture, strategies, and comprehensive test plans.
• Code, execute, and debug test cases to achieve functional and code coverage goals.
• Handle verification of complex subsystems independently to ensure successful Si realization.
• Collaborate with cross-functional teams including Architecture, Design, and external customers.
• Mentor and coach junior engineers to develop their technical independence.

Requirements

• Extensive experience in Subsystem and SOC level verification projects.
• In-depth knowledge of SystemVerilog (SV) and UVM.
• Experience with ARM-based designs and AMBA protocols (AXI, ACE, APB, AHB).
• Proficiency in C-based testcase development.
• Knowledge of high-speed protocols such as USB, PCIe, Ethernet, DDR, or LPDDR.
• Strong communication and organizational skills for stakeholder management in Austin, TX.

Nice to have

• Prior experience with hirify.global tools and flows.
• Experience with assembly language programming and Embedded C.
• Knowledge of UART, I2C, SPI, or JTAG protocols.
• Experience with Formal Verification.

Culture & Benefits

• Opportunity to work on impactful technology that solves complex engineering challenges.
• Fast-paced, dynamic project environment.
• Collaborative team culture focusing on leadership and innovation.