IP Design Verification Engineer

TL;DR

IP Design Verification Engineer (LPDDR5/DDR5): Verify functionality and performance of hirify.global's IP designs for SoC applications with an accent on RTL validation, protocol compliance, and coverage closure. Focus on developing UVM testbenches, debugging failures, and automating validation flows for next-generation memory PHYs.

Location: Hybrid in Penang, Malaysia

Company

hirify.global's Central Engineering Group builds scalable solutions for IP enablement, custom ASIC, and foundry services.

What you will do

• Own RTL validation for functional and DFx features using OVM/UVM testbenches.
• Define verification strategies, test plans, BFMs, assertions, and coverage.
• Perform gate-level simulations, debug failures, and analyze coverage metrics.
• Automate pre-silicon flows with Tcl, Perl, or Python scripts.
• Collaborate with architects, RTL developers, and SoC teams on IP integration.
• Maintain and enhance verification methodologies and infrastructure.

Requirements

• Bachelor's or advanced degree in Electrical/Computer Engineering or related.
• 6+ years experience (Bachelor's), 4+ (Master's), 2+ (PhD).
• Strong SystemVerilog, OVM/UVM proficiency.
• Expertise in DDR/LPDDR5 protocols across validation stages.
• RTL validation, logic design, DFx, debug skills.
• Experience with VCS, Verdi, UNIX, shell scripting, C.

Nice to have

• IP validation across full project lifecycles.
• Advanced debugging and formal verification skills.
• Automation with Tcl, Tk, Perl, Python.
• Strong communication for cross-functional collaboration.

Culture & Benefits

• Hybrid work model splitting time between on-site in Penang and off-site.
• Dynamic, innovative team shaping computing technologies.
• Collaboration with global architects and developers.
• Focus on customer-driven solutions with short cycles.