Staff Engineer, Design Verification (ASIC)

TL;DR

Staff Engineer, Design Verification (ASIC): Developing and executing verification plans for high-speed SerDes PHY and digital circuits in high-speed data communication ICs with an accent on UVM methodology and SystemVerilog. Focus on block and chip-level verification, modeling, and ensuring the functionality of PCIE and Ethernet IPs.

Location: Hsinchu, Taiwan

Company

hirify.global is a leading provider of semiconductor solutions for data infrastructure, cloud, and AI architectures.

What you will do

• Develop verification plans, test environments, and models for digital circuits in high-speed data communication ICs.
• Execute block and chip-level verification for PCIE, Ethernet, and SerDes PHY functions.
• Implement verification flows using UVM methodology and SystemVerilog.
• Conduct Digital-Analog-Mixed simulations and develop UVM AMS models.
• Collaborate with the Central System Engineering team to ensure smooth SoC production.

Requirements

• Bachelor's degree in CS, EE, or related (7-8 years exp) or Master's/PhD (5-6 years exp).
• Strong proficiency in UVM/OVM/VMM and SystemVerilog/Verilog.
• Knowledge of C, C++, and System C.
• Experience with random techniques and coverage-driven verification flows.
• Ability to use scripting languages including Perl, Python, Makefile, and C Shell.
• Must be eligible to access export-controlled information under U.S. export control laws (EAR).

Culture & Benefits

• Competitive compensation and comprehensive benefits package.
• Work environment centered on shared collaboration, transparency, and inclusivity.
• Access to tools and resources for professional growth and career development.

Hiring process

• Interviews focused on individual experience, thought process, and real-time communication.
• Strict prohibition of AI tools (ChatGPT, Copilot, transcription apps) during the interview process; use results in disqualification.