Fall 2026 Co-Op - Mixed Signal Modeling & Verification Engineer (ASIC)

TL;DR

Fall 2026 Co-Op - Mixed Signal Modeling & Verification Engineer (ASIC): Developing and validating SystemVerilog models for audio processing ASICs with an accent on top-down design methodology and AMS/UVM verification. Focus on interpreting analog circuit schematics into abstract models and performing regression debug support.

Location: Austin, Texas. Must be based within commutable distance or be willing to relocate

Company

hirify.global is a leader in mixed-signal processing, creating innovative audio solutions for the world's top consumer brands.

What you will do

• Perform verification planning and AMS simulation on full custom ASICs for audio processing applications.
• Develop behavioral models using SystemVerilog real number modeling (sv-rnm), user-defined types (sv-udt), and Verilog AMS.
• Interpret analog circuit schematics into abstract models independently.
• Provide regression debug support and contribute to flow and infrastructure development.
• Collaborate with systems and design teams to facilitate top-down design methodology.

Requirements

• Currently pursuing a Bachelors, Masters, or PhD in Electrical Engineering or Computer Engineering.
• Strong understanding of analog integrated circuit design.
• Experience with SystemVerilog RNM and/or Verilog-A behavioral modeling.
• Must be based in or willing to relocate to Austin, Texas.
• Must be able to access technical data without a requirement for an export license.

Culture & Benefits

• Award-winning culture focused on inclusion, fairness, and meaningful community engagement.
• Collaborative, fast-paced, and supportive environment for professional growth.
• Hybrid work schedule (interns may be required in-office up to 5 days per week based on business needs).