Design Verification Engineer

TL;DR

Design Verification Engineer (Networking ASICs): Verifying L2/L3 network switching and routing ASICs supporting hundreds of Terabits/sec traffic with an accent on traffic management, scheduling, shaping, latency, and performance characterization. Focus on developing in-depth test plans, SystemVerilog testbenches, verification APIs, and achieving functional/code coverage closure pre-silicon.

Location: USA - CA, San Jose (onsite, full-time)

Salary: $120,000 - $192,000 annual base

Company

hirify.global's CSG group develops cutting-edge Tomahawk ASICs for Scale-Out and Scale-Up AI Networks supporting latest protocols, high-speed ports up to 1600Gb/s, and massive traffic volumes.

What you will do

• Participate in verification of L2/L3 Network Switching and routing ASICs and subsystems.
• Understand chip architecture and develop detailed test plans for key networking features like traffic streaming, management, scheduling, shaping, latency, and performance.
• Build verification environments including testbenches, APIs, scripts, and Makefiles for various toolchains.
• Implement test suites using SystemVerilog/UVM and execute verification to completion with coverage metrics.

Requirements

• MSEE/BSEE or equivalent with 8+ years (BS), 6+ years (MS), or 3+ years (PhD) in digital design.
• Familiarity with Verilog/SystemVerilog/UVM, Perl/Python scripting, and OOP.
• Experience with advanced verification methodologies and end-to-end process from test plans to coverage closure on production ASICs/SoCs.
• Strong verbal and written communication skills.

Culture & Benefits

• Competitive base salary, discretionary annual bonus, new hire and annual equity awards.
• Comprehensive benefits: medical, dental, vision, 401(k) with matching, ESPP, EAP, paid holidays, sick leave, vacation, Paid Family Leave.
• Equal opportunity employer considering qualified applicants without regard to protected characteristics.