Mixed-Signal IC Layout Design Engineer (AI)

TL;DR

Mixed-Signal IC Layout Design Engineer (Analog/Mixed-Signal): Developing full-custom physical layouts for high-speed analog and mixed-signal blocks for advanced AI platforms with an accent on FinFET processes and SoC integration. Focus on optimizing parasitics, ensuring reliability (EM/IR, ESD), and achieving physical verification closure for high-performance silicon.

Location: Remote (Must be based in the United States)

Salary: $100k - $500k

Company

hirify.global is an AI technology leader developing high-performance RISC-V CPUs and cutting-edge AI platforms.

What you will do

• Execute full-custom analog/mixed-signal layout for key blocks including PLLs, VCOs, ADCs, DACs, and high-speed I/Os.
• Develop optimized block and top-level floorplans, placement, and routing to balance area, parasitics, and matching.
• Optimize R/C parasitics, coupling, IR drop, and electromigration to meet precision, noise, and timing goals.
• Ensure physical verification closure by closing DRC, LVS, ERC, DFM, and Antenna requirements.
• Support post-layout extraction and simulation.
• Contribute to layout methodology and automation via Python, Tcl, or SKILL scripts.

Requirements

• Strong background in full-custom layout of high-speed analog/mixed-signal blocks.
• Proficiency with Synopsys Custom Compiler or Cadence Virtuoso.
• Experience with physical verification tools such as Synopsys ICV or Siemens Calibre.
• Deep experience in CMOS/FinFET nodes (ideally TSMC or Samsung 12nm–2nm) with delivered silicon.
• Solid understanding of EM/IR, ESD, and latch-up in mixed-signal layouts.
• Must be eligible to access U.S. export-controlled technology (contingent upon citizenship/permanent residency or license approval).

Culture & Benefits

• Highly competitive compensation package and benefits.
• Opportunity to work with cutting-edge FinFET technologies down to 2nm.
• Hands-on experience integrating high-speed analog/mixed-signal IP into complex D2D PHY.
• Collaborative environment focused on solving hard problems and evolving layout methodologies.