Design Verification Engineer (VLSI)

TL;DR

Design Verification Engineer (VLSI): Verifying circuitry for semiconductor chips used in enterprise, cloud, and AI data infrastructure with an accent on UVM environment development and test plan definition. Focus on achieving 100% verification coverage, debugging simulation failures, and ensuring designs meet customer specifications.

Location: Santa Clara, CA or Irvine, CA

Salary: $86,950 - $130,100 per annum

Company

hirify.global provides essential semiconductor solutions that serve as building blocks for data infrastructure across enterprise, cloud, and AI.

What you will do

• Develop and maintain verification environments using UVM.
• Define and review verification test plans with architecture and design teams.
• Verify designs using randomized functional parameters.
• Run regressions and debug failures in the simulation environment.
• Monitor and drive verification coverage toward a 100% goal.
• Understand and analyze PCIE and Memory architecture/functionality.

Requirements

• Bachelor's degree in Electrical or Computer Engineering (1-3 years experience) or a Master's degree.
• Coursework in analog classes, Verilog or VHDL, basic circuits, and computer architecture with a focus on VLSI.
• Experience using simulation tools such as Synopsys, Cadence, or Mentor to write and debug testbenches.
• Proficiency in Linux environments and Python scripting.
• Must be eligible to access export-controlled information as defined under applicable U.S. law.

Culture & Benefits

• Employee stock purchase plan with a 2-year look back.
• Comprehensive family support programs to balance work and home life.
• Robust mental and physical health resources.
• Recognition and service awards for contributions and milestones.
• Comprehensive benefits supporting employees from internship to retirement.