Analog Circuit Design Engineer (Hardware)

TL;DR

Analog Circuit Design Engineer (Analog/RF): Designing critical foundational collateral on leading-edge hirify.global processes to meet density and performance scaling goals for CPU and SoC products with an accent on passive components such as MFC, TFR, and inductors. Focus on co-optimizing design and technology (DTCO), ensuring high-quality PDK releases, and delivering silicon-proven solutions through test chips.

Location: Hybrid. Must be based in or be able to work from Hillsboro, OR; Santa Clara, CA; or Phoenix, AZ

Salary: $141,910 - $269,100

Company

hirify.global Foundry develops state-of-the-art semiconductor manufacturing and packaging technology to enable leadership products for the AI era.

What you will do

• Drive on-time library PDK releases and coordinate with stakeholders in device, integration, and OPC for customer solutions.
• Define and design copy-exact foundational IP for passive components (MFC, TFR, inductors, varactors) to optimize performance and area.
• Co-optimize design, process modeling, and design rules as part of DTCO in collaboration with process device and reliability stakeholders.
• Design library collateral schematics and layouts for passive components and characterize them via electrical parameter extraction flows.
• Develop and maintain template design guidelines and best practices across different process nodes.
• Collaborate with modeling teams to ensure the accuracy of electrical models for designed templates.

Requirements

• Bachelor's degree in Electrical Engineering or STEM field with 4+ years of experience (Master's: 3+ years, Ph.D.: 6+ months) in analog/RF circuit design or device physics.
• 3+ years of experience with SPICE level circuit design/simulation and Cadence Virtuoso, including layout generation.
• 3+ years of experience in data analysis or scripting using Python or Matlab.
• Must be based in the United States (Oregon, California, or Arizona).

Nice to have

• Experience with device physics, analog fundamentals (gain, bandwidth, noise, linearity, stability), and yield analysis (Monte Carlo).
• Knowledge of electromagnetic simulation tools and RF design principles.
• Familiarity with Pcell design using SKILL.
• Exposure to post-silicon characterization and debug.
• Familiarity with statistics/DOE and machine learning for design space exploration.

Culture & Benefits

• Hybrid work model allowing split time between on-site and off-site work.
• Total compensation package including competitive pay and stock bonuses.
• Comprehensive benefit programs including health, retirement, and vacation.