Senior Physical Design Engineer (AI)

TL;DR

Senior Physical Design Engineer (AI): Driving chiplet-level and chip-top physical implementation of high-performance CPU-based SoCs in a cutting-edge system-in-package environment with an accent on PPA closure and timing. Focus on floorplanning, integration of multi-chiplet systems, and full physical verification in advanced nodes (5nm and below).

Location: Hybrid, based out of Tokyo, Japan

Company

hirify.global is leading the industry on cutting-edge AI technology, developing high-performance RISC-V CPUs and unified AI platforms.

What you will do

• Lead chiplet and chip-top implementation for high-profile, multi-chiplet System-in-Package projects.
• Perform place and route for high-speed CPU core designs in advanced nodes (5nm and below).
• Own chip-top floorplanning and integration, including BUS, fabric planning, and IO placement.
• Drive full physical verification and convergence, covering DRC/LVS, noise, and electromigration checks.
• Manage chip-level synthesis and provide technical leadership and mentoring to junior team members.

Requirements

• Bachelor’s, Master’s, or PhD in electrical engineering, computer engineering, or computer science.
• Extensive experience (typically 10+ years) in SoC/ASIC/GPU/CPU physical design on taped-out designs.
• High proficiency with industry-standard tools such as Synopsys and Cadence.
• Ability to script in TCL and at least one other language (e.g., Python).
• Must be eligible to access U.S. export-controlled technology (compliance with U.S. EAR regulations regarding citizenship/permanent residency).

Culture & Benefits

• Highly competitive compensation package and benefits.
• Collaborative global environment partnering with experts across Japan, the USA, and other regions.
• Opportunity to work on ground-breaking RISC-V CPU technology.
• Company culture that values curiosity and a commitment to solving hard problems.