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3 дня назад

Power Design Engineer (AI)

Формат работы
hybrid
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
Japan
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

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TL;DR

Power Design Engineer (AI): Designing and optimizing power analysis and projections for high-performance CPU chiplets within a System-in-package (SiP) architecture with an accent on power rail planning and PDN optimization. Focus on driving power analysis on RTL and Netlist, optimizing power vectors, and correlating pre-silicon projections with silicon measurements.

Location: Hybrid, based out of Tokyo, Japan

Company

Leading the industry in cutting-edge AI technology by developing high-performance RISC-V CPUs and AI platforms.

What you will do

  • Own power analysis and projections for CPU chiplets, tracking metrics throughout the design cycle.
  • Define and maintain the power vector plan for comprehensive chiplet-level and chip-level coverage.
  • Drive power analysis on RTL and netlist using tools such as Joules and PrimePower.
  • Partner with RTL design, synthesis, and physical design teams to measure and optimize power.
  • Evaluate and propose new power optimization techniques and implement changes via timing ECOs.
  • Correlate pre-silicon power models with real silicon behavior to improve next-generation architectures.

Requirements

  • 10+ years of experience in ASIC or related design.
  • Extensive experience in power analysis and optimization for complex ASICs.
  • Proficiency with power analysis tools (e.g., Joules, PrimePower).
  • Strong scripting skills in Tcl and Python (or similar).
  • Must be eligible to access U.S. export-controlled technology (contingent upon citizenship/residency status per EAR regulations).

Nice to have

  • Familiarity with UPF/CPF low-power intent.
  • Knowledge of Verilog/SystemVerilog.
  • Understanding of CPU micro-architecture and its power challenges.
  • Basic thermal analysis experience.

Culture & Benefits

  • Opportunity to work on a 2nm CPU chiplet within a multi-chiplet SiP.
  • Collaboration with worldwide experts across the USA, Japan, and other countries.
  • Engagement with high-profile projects backed by the Japanese government's investment packages.
  • Collaborative and curious environment focused on solving hard technical problems.

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