Junior Digital Verification (Embedded)

TL;DR

Junior Digital Verification (Embedded): Developing and implementing testbenches for digital IP blocks and sub-systems with an accent on functional correctness and coverage. Focus on debugging design issues, creating test plans, and ensuring thorough testing of complex integrated circuits.

Location: Catania, Italy

Company

World leader in secure connectivity solutions for embedded applications, pushing boundaries in automotive, industrial, IoT, and communication infrastructure markets.

What you will do

• Develop and implement testbenches and verification environments for digital IP blocks and sub-systems.
• Create and execute test plans, test cases, and functional coverage models.
• Debug design issues and collaborate with design engineers to achieve functional correctness.
• Analyze verification results and generate coverage reports to ensure thorough testing.
• Participate in verification methodology development and continuous improvement efforts.
• Document verification processes, results, and findings clearly and concisely.

Requirements

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
• Basic understanding of digital design concepts and HDL languages (Verilog/SystemVerilog).
• Strong analytical and problem-solving skills with attention to detail.
• Excellent communication and teamwork skills.
• Proactive attitude and eagerness to learn in a fast-paced environment.

Nice to have

• Familiarity with UVM methodology.
• Knowledge of scripting languages such as Python or Perl.

Culture & Benefits

• Online and offline learning opportunities to develop core and professional skills.
• Inclusive work environment with a strong commitment to diversity, equality, and non-discrimination.
• Company-wide focus on sustainability and measurable year-on-year progress.