SOC Design Verification Engineer (Semiconductor)

TL;DR

SOC Design Verification Engineer (SystemVerilog/UVM): Researching, designing, and testing next-generation Client SOCs for laptops and desktops with an accent on system-level validation and microarchitecture debugging. Focus on implementing validation plans, debugging RTL models, and developing tools to streamline SOC integration.

Location: Hybrid; must be based in Hillsboro, Oregon, USA

Salary: $122,440 - $232,190

Company

Leading global semiconductor company designing next-generation computing experiences and world-changing technology.

What you will do

• Validate IPs and features at the system or subsystem level.
• Create validation plans and tests for complex microarchitectures using RTL code and technical specs.
• Debug failures to the root cause to analyze and refine architecture.
• Develop debug and validation tools to ensure design robustness.
• Collaborate with IP providers and customers to define and deliver necessary infrastructure.
• Develop software tools and methods to streamline SOC integration and IP development.

Requirements

• BS + 3 years or MS + 2 years of experience in Computer Science, Computer Engineering, or Electrical Engineering.
• Minimum 2 years of experience reading and interpreting technical specs and Register Transfer Level (RTL) code.
• Minimum 2 years of experience in IP or SoC development/verification using Verilog/SystemVerilog and OVM/UVM.
• Experience writing validation plans and software to implement them.
• Proficiency in an object-oriented programming language and Verilog or other HDL.
• At least 1 year of experience with UNIX or Linux.

Nice to have

• Experience with computer architecture.
• 3+ years of validation or testing experience, particularly within a silicon design team.

Culture & Benefits

• Competitive pay and stock bonuses.
• Comprehensive benefit programs including health, retirement, and vacation.
• Hybrid work model allowing employees to split time between on-site and off-site work.