Principal Verification Engineer (SoC)

TL;DR

Principal Verification Engineer (SoC/UVM): Verifying circuitry for high-speed chips used in AI, cloud data centers, and telecom with an accent on simulation test benches and design correctness. Focus on implementing UVM test benches, debugging simulation failures, and mentoring junior engineers to ensure hardware specifications are met.

Location: Santa Clara, CA

Salary: $158,600 – $237,600 per annum

Company

hirify.global provides essential semiconductor solutions for data infrastructure across enterprise, cloud, and AI architectures.

What you will do

• Implement simulation test benches in UVM.
• Develop and execute test plans for verifying design correctness and performance.
• Own and debug simulation failures to root-cause problems.
• Collaborate with logic designers on test plan development, execution, coverage closure, and gate-level simulations.
• Coach and mentor junior engineers to achieve successful project outcomes.

Requirements

• Bachelor's degree (7+ years experience) or Master's degree (5+ years experience) in Computer Science, Electrical Engineering, or related fields.
• Strong background in SoC verification and test bench development using UVM, SystemVerilog, C++, and DPI.
• Deep understanding of verification methodology (OOP, white-box/black-box, directed/random testing, coverage, and gate-level simulations).
• Proven ability to analyze datasets and draw valid conclusions to define problems and opportunities.
• Must be eligible to access export-controlled information as defined under applicable U.S. law.

Culture & Benefits

• Employee stock purchase plan with a 2-year look back.
• Comprehensive family support programs to balance work and home life.
• Robust mental and physical health resources.
• Recognition and service awards to celebrate contributions and milestones.