Senior Engineer, Analog Layout (Semiconductors)

TL;DR

Senior Engineer, Analog Layout (Semiconductors): Developing General Purpose IOs (GPIO) and IO ESD solutions across various process nodes for hyperscale datacom centers with an accent on physical layout and verification of high-speed I/O circuits. Focus on implementing ESD/LUP rules, releasing I/O IP libraries, and conducting peer-to-peer layout quality checks.

Location: Singapore

Company

hirify.global provides semiconductor solutions that serve as essential building blocks for data infrastructure across enterprise, cloud, and AI architectures.

What you will do

• Perform physical layout and verification of high-speed I/O circuits, General Purpose I/Os, and ESD structures using Cadence tools.
• Collaborate with ESD leads to support worldwide IP/SoC ESD/LUP DRC/ERC reviews.
• Implement ESD/LUP rules for different process nodes in coordination with the CAD team.
• Manage the release of I/O IP libraries and perform layout quality checks.
• Contribute to the team through tool testing, script development, and flow documentation.

Requirements

• Bachelor’s or Master's degree in Electrical Engineering, Computer Science, or related fields.
• 3+ years of professional experience in analog mixed-signal layout.
• High proficiency in Synopsys or Cadence layout entry tools.
• Strong ability to interpret CALIBRE DRC, ERC, and LVS reports.
• Must be eligible to access export-controlled information as defined under U.S. export control laws.

Nice to have

• Experience with FinFet layout.
• Knowledge of ESD and latch-up.
• Scripting skills in PERL, TCL, or SKILL.

Culture & Benefits

• Competitive compensation package and comprehensive benefits.
• Environment defined by shared collaboration, transparency, and inclusivity.
• Access to professional tools and resources for career growth and development.