Principal SoC Architect (AI)

TL;DR

Principal SoC Architect (AI): End-to-end SoC architecture for AI inference platform with an accent on key SoC blocks, interfaces, memory subsystems, and interconnects. Focus on making trade-offs under PPA constraints, designing control paths, and collaborating across RTL, firmware, validation, and bring-up teams for silicon performance tuning.

Location: Onsite in Santa Clara, CA; New York City, NY; or San Francisco, CA

Company

Early-stage startup backed by Tier-1 VC innovating at chip and system level for order-of-magnitude better performance-per-watt in AI inference.

What you will do

• Architect end-to-end SoC for AI inference platform including key blocks and interfaces
• Design HBM/LPDDR memory subsystems, bandwidth modeling, and memory controller integration
• Develop control path including CPU complex, boot flows, security, power/reset/clocking
• Make trade-offs under constraints like PPA, schedule, and cost
• Collaborate closely with RTL, firmware, validation, and packaging teams
• Define silicon bring-up, debug strategy, and performance tuning

Requirements

• Architected real, shipping SoCs
• Strong knowledge of key SoC blocks and their interfaces
• Experience across architecture, RTL, firmware, bring-up teams and full SoC life cycle
• Worked with PCIe Gen5 or higher, scale-up/scale-out interconnects, UCIe integration
• Experience with HBM/LPDDR memory subsystem architecture and controller integration
• Comfortable with control path design and cross-team collaboration

Nice to have

• Early-stage SoC development in startup environment
• Chiplet or multi-die SoCs
• AI accelerators, GPUs, or high-bandwidth networking silicon