Senior ASIC Design Engineer

TL;DR

Senior ASIC Design Engineer (Networking): Implement RTL designs using Verilog/SystemVerilog for high-speed data paths and packet processing logic in SoCs for AI and HPC interconnects with an accent on Ethernet protocols, Host Fabric Interfaces, and performance optimization. Focus on defining timing constraints, collaborating on verification and physical design, and supporting post-silicon validation to resolve issues.

Location: Remote position for employees residing within the United States.

Company

Delivering high-performance scale-out networking solutions for AI and HPC datacenters, integrating hardware, software, and system technologies.

What you will do

• Implement RTL designs using Verilog/SystemVerilog for high-speed data paths and packet processing logic.
• Collaborate with verification engineers on block- and system-level test plans for comprehensive coverage.
• Define timing constraints for RTL blocks and work with Physical Design engineers on timing closure.
• Support post-silicon validation, debugging ASIC issues with hardware, firmware, and software teams.
• Contribute to performance optimization and power-aware design for Host Fabric Interface subsystems.

Requirements

• B.S. or M.S. in Computer Engineering, Electrical Engineering, or related field.
• 8+ years in digital design with proficiency in Verilog and SystemVerilog.
• Experience in RTL design for high-speed data paths or packet processing in ASICs.
• Deep understanding of Host Ethernet adapter architectures.
• Familiarity with timing closure and modern physical design methodologies.
• Proven system-level debug and root cause analysis skills.
• Strong verbal and written communication skills.

Nice to have

• Knowledge of Ethernet architecture and networking protocols (TCP/IP, RDMA/RoCE, IPSec).
• Prior RTL development for Ethernet host adapters and system debug.
• Expertise in multiple clock domain designs and asynchronous interfaces.
• 5+ years with scripting languages (TCL, Python, Perl).
• Familiarity with EDA tools (Design Compiler, Spyglass, PrimeTime).

Culture & Benefits

• Competitive compensation with equity, cash, incentives, medical, dental, vision coverage.
• 401(k) with company match, Open Time Off (OTO), sick time, bonding leave, pregnancy disability leave.
• Flexible work environment with onsite, hybrid, and fully remote roles across multiple U.S. states and countries.
• Opportunity to collaborate with influential names in the semiconductor industry.