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1 день назад

Senior Digital / RTL Design Engineer (SystemVerilog)

Формат работы
remote (только Europe)/hybrid
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
Italy/Germany/Austria +1 еще
Релокация
Germany/Austria
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

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TL;DR

Senior Digital / RTL Design Engineer (SystemVerilog): Developing high-performance network solutions and digital IP blocks from specification to implemented netlist with an accent on microarchitecture and chip-level integration. Focus on translating complex industry standards into RTL, debugging functional errors, and optimizing SerDes interconnect technologies.

Location: Hybrid in Mannheim (Germany) or Villach (Austria); Remote available for candidates based in Germany, Austria, Italy, or Greece. Relocation and visa support provided for eligible candidates.

Company

Leader in state-of-the-art High-Speed Serializer-Deserializer (SerDes) IP and interconnect technologies for semiconductor chips.

What you will do

  • Analyze complex design specifications and industry standards to create microarchitecture specifications.
  • Develop and maintain complex digital IPs at the RTL level, taking ownership of IP blocks and sub-blocks.
  • Support digital IPs from inception through design, verification, tape-out, and bring-up.
  • Collaborate with functional verification teams to debug identified errors.
  • Create internal and customer-facing product specification documentation.
  • Coordinate with architecture, verification, backend, and firmware teams to ensure on-time product release.

Requirements

  • B.S./M.S. degree in Electrical Engineering, Physics, Computer Engineering, or Information Technology.
  • Minimum 5 years of work experience in hardware design (including internships).
  • Proficiency in HDL design, preferably using SystemVerilog.
  • Experience with Cadence XCELIUM or comparable simulators.
  • English: Good written and oral communication skills required.
  • Location: Must be based in or be able to relocate to Germany, Austria, Italy, or Greece.

Nice to have

  • Knowledge of timing constraints and synthesis.
  • Knowledge of functional verification (UVM) and SystemVerilog assertions.
  • Experience with communication protocols such as UCIe, PCIe, Ethernet, AMBA AXI, or CHI.
  • Scripting skills in Python for automation tasks.
  • German language proficiency.

Culture & Benefits

  • Flexible working hours (flextime) and above-average annual vacation.
  • Hybrid and remote work options, including "workation" for up to six weeks per year in another country.
  • Competitive salary based on qualifications in a financially strong company.
  • Opportunities for career growth, professional development, and continuous training.
  • Supportive atmosphere with employee events, gaming tournaments, and free drinks.

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