ASIC Design Engineer (AI)

TL;DR

ASIC Design Engineer (AI): Building high-performance scale-out networking solutions for AI and HPC datacenters with an accent on advanced ethernet protocols and micro-architecture specifications. Focus on implementing RTL blocks, optimizing timing constraints, and resolving post-silicon ASIC issues.

Location: Remote from Costa Rica via EOR

Company

hirify.global delivers high-performance scale-out networking solutions for AI and HPC datacenters using an AI-first approach to silicon and software.

What you will do

• Implement advanced ethernet protocols for next-generation ethernet ASICs.
• Write detailed micro-architecture specifications.
• Define timing constraints for RTL blocks and collaborate with Physical Design engineers for optimization.
• Work with verification engineers to create block/system level test plans and ensure design coverage.
• Collaborate with hardware, firmware, and software engineers to resolve post-silicon ASIC issues.

Requirements

• B.S. or M.S. degree in Computer or Electrical Engineering.
• 10+ years of post-college experience in digital design.
• Proficiency in Verilog and System Verilog.
• Experience in timing closure and familiarity with modern physical design methodologies.
• Strong system-level debug skills and ability to determine root causes of technical issues.
• Strong verbal and written communication skills.

Nice to have

• Experience with Ethernet architecture and Networking protocols.
• Experience designing ethernet protocols for adapters and switches.
• Experience with multiple clock designs and asynchronous interfaces.

Culture & Benefits

• Comprehensive total rewards package including base salary.
• Eligibility for performance-based incentives and annual bonuses.
• Opportunity to work in a fast-growing, forward-thinking global organization.
• Collaborative environment spanning multiple countries and US states.