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8 часов назад

Senior DFT Timing Signoff Engineer (STA)

164 470 - 269 100$
Формат работы
hybrid
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify RU Global, списка компаний с восточно-европейскими корнями
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Мэтч & Сопровод

Для мэтча с этой вакансией нужен Plus

Описание вакансии

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TL;DR

Senior DFT Timing Signoff Engineer (STA): Owning DFT-mode timing constraints and PrimeTime STA signoff for next-generation AI processors with an accent on Tessent DFT architecture including SSN, IJTAG/HTAP/TAPLink, and MBIST/BISR. Focus on establishing constraints hygiene, debugging integration issues, driving backend closure, and automating flows for first-pass silicon success.

Location: US, California, Folsom (hybrid work model: split time on-site at hirify.global site and off-site)

Salary: $164,470.00-269,100.00

Company

hirify.global designs and manufactures silicon products for data centers, AI-accelerated systems, HPC, and general-purpose compute.

What you will do

  • Own definition, generation, validation, and maintenance of DFT timing constraints (SDC) in PrimeTime for scan, JTAG/IJTAG, and memory BIST modes.
  • Perform PrimeTime STA signoff for DFT modes at block and top levels across corners, ensuring coverage and exception governance.
  • Enforce constraints hygiene standards including mode separation, audits, linting, and regressions.
  • Collaborate with DFT architecture/implementation on SSN, IJTAG, HTAP/TAPLink, MBIST integration and translate into timing constraints.
  • Debug DFT insertion issues in RTL/gate-level netlists and drive timing convergence with PD/CTS/PnR teams via ECOs.
  • Automate DFT/STA flows (Tcl/Python) and develop signoff checklists/reporting for stakeholders.

Requirements

  • Bachelor's +8 years or Master's +6 years in Electrical/Computer Engineering
  • 6+ years DFT/STA for complex SoCs with PrimeTime signoff and constraints ownership
  • Tessent DFT concepts: SSN, IJTAG/HTAP/TAPLink, MBIST/BISR
  • CDC/RDC fundamentals, Verilog/SystemVerilog for netlist debugging
  • Tcl required; Python/shell preferred

Nice to have

  • Hands-on Tessent flow experience in hierarchical SoCs
  • Signoff hygiene for scan/MBIST/JTAG in MMMC environments
  • Quality checks: lint, CDC/RDC, LEC, Spyglass DFT
  • Cross-team closure under aggressive schedules

Culture & Benefits

  • Competitive pay, stock bonuses, health, retirement, vacation benefits
  • Hybrid work model
  • Shift 1 (United States of America)

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