Staff Design for Test Engineer (AI)

TL;DR

Staff Design for Test Engineer (AI): Implementing and integrating DFT features for high-performance AI/ML architectures with an accent on reducing test cost and attaining high coverage. Focus on owning ATPG, test coverage analysis, and refining DFx methodologies to ensure first-pass silicon success on advanced nodes.

Location: Hybrid, based out of Santa Clara, CA or Austin, TX

Compensation: $100k - $500k

Company

hirify.global is developing cutting-edge AI technology and high-performance RISC-V CPUs to redefine the computing paradigm.

What you will do

• Implement and integrate DFT features such as scan, JTAG, compression, ASST, and MBIST from early design through tapeout.
• Own ATPG and test coverage analysis, utilizing gate-level simulation with Synopsys VCS/Verdi.
• Plan and verify MBIST and collaborate with Test Engineering on pattern delivery and debug.
• Develop and refine DFx flows and methodologies to balance coverage, test cost, and design intrusiveness.

Requirements

• BS/MS/PhD in EE/ECE/CE/CS with 5+ years of industry experience in advanced DFx/DFT for complex ASIC/SoC designs.
• Proficiency in Verilog RTL for DFT logic and experience with SystemVerilog/UVM.
• Hands-on experience with ATPG, DFx insertion tools, and fault models (Stuck-at, Transition, Path Delay, IDDQ, Cell-Aware).
• Strong debug skills across design hierarchies and ability to collaborate with PD, verification, and test teams.
• Must be eligible to access U.S. export-controlled technology (EAR compliance).

Culture & Benefits

• Highly competitive compensation package and benefits.
• Collaborative environment focused on solving hard problems in AI hardware.
• Opportunity to work with a senior, cross-functional ASIC team on advanced nodes.