Staff Engineer, SoC - DFD Design Verification (AI)

TL;DR

Staff Engineer, SoC - DFD Design Verification (AI): Pre-silicon verification of DFD logic in advanced AI SoCs with an accent on debug, test, and bring-up features. Focus on developing verification environments for chiplets, executing test scenarios for scan and MBIST, and automating JTAG/scanchain testing.

Location: Hybrid; must be based in Boston, MA; Toronto, Ottawa; or Santa Clara, CA

Compensation: $100k - $500k (including base and variable targets)

Company

hirify.global is leading the industry on cutting-edge AI technology, unifying innovations in software models, compilers, and semiconductors to build the best AI platform possible.

What you will do

• Develop and own verification environments for DFD logic across AI chiplets and SoCs.
• Write, refine, and execute test scenarios for scan, MBIST, array dump, and clock-stop features.
• Analyze coverage gaps, debug failures, and collaborate closely with DFT and RTL teams.
• Automate flows for JTAG/scanchain testing and integrate AI productivity tools.

Requirements

• Expertise in UVM and verification of DFT/DFD features, scan, and on-chip trace logic.
• Proficiency with Siemens Tessent flows, iJTAG, and advanced verification automation.
• Must be eligible to access U.S. export-controlled technology (compliance with EAR laws).
• Ability to thrive in cross-functional technical discussions.

Nice to have

• Familiarity with tools similar to CocoTB.

Culture & Benefits

• Highly competitive compensation package and comprehensive benefits.
• Opportunity to work on a high-performance RISC-V CPU developed from scratch.
• Environment that values collaboration, curiosity, and solving hard problems.
• Equal opportunity employer.