Static Timing Analysis (STA) Methodology Engineer (AI)

TL;DR

Static Timing Analysis (STA) Methodology Engineer (AI): Developing and optimizing end-to-end STA methodologies for high-performance, low-power AI hardware with an accent on PrimeTime and ML-assisted timing automation. Focus on improving PPA, resolving complex timing correlation issues, and architecting scalable CAD utilities.

Location: Hybrid: Must be based in Santa Clara, CA, Austin, TX, or Fort Collins, CO

Salary: $100k - $500k

Company

hirify.global is leading the industry in cutting-edge AI technology, developing high-performance RISC-V CPUs and AI platforms.

What you will do

• Own timing across advanced-node, high-performance, and low-power designs.
• Lead the development and optimization of end-to-end STA methodologies and flows from RTL to GDS.
• Drive data- and ML-assisted timing automation to improve PPA and runtime efficiency.
• Partner with logic, physical design, DFT, and EDA vendors to solve complex timing challenges.
• Architect and maintain production STA flows and scalable CAD utilities.

Requirements

• BS/M in Electrical or Computer Engineering or equivalent experience.
• 5+ years of industry experience focusing on high-performance and low-power designs at advanced technology nodes.
• Deep expertise with PrimeTime and signoff tools (PT-SI, PTPX, PT-ECO).
• Proficiency in writing production-quality scripts using Tcl, Python, and/or Perl.
• Must be eligible to access U.S. export-controlled technology (EAR compliance).

Culture & Benefits

• Highly competitive compensation package and benefits.
• Opportunity to work in a rapidly evolving startup environment.
• Direct influence on tool roadmaps through partnerships with leading EDA vendors.
• Collaborative culture focused on solving hard technical problems.