Physical Design Timing Engineer (STA)

TL;DR

Physical Design Timing Engineer (STA): Ensuring ASIC performance targets and timing requirements across all operating conditions with an accent on MMMC analysis and SDC constraint development. Focus on implementing timing ECOs and resolving complex timing issues in partnership with cross-functional teams.

Location: USA, San Jose, CA (Onsite)

Salary: $141,300 – $226,000

hirify.global is a global technology leader that designs, develops, and supplies semiconductor and infrastructure software solutions.

What you will do

• Own full-chip timing sign-off and ensure ASIC performance goals across PVT corners.
• Author, validate, and maintain SDC for various functional and test modes.
• Manage MMMC analysis for hundreds of timing scenarios to ensure reliability.
• Automate, generate, and implement timing ECOs to resolve setup, hold, and transition violations.
• Develop and maintain scripting flows using Tcl, Python, and Perl.
• Partner with RTL, Physical Design, and DFT teams to resolve complex timing and guard-banding challenges.

Requirements

• Bachelor’s degree in Electrical Engineering or Computer Engineering.
• Minimum 12 years of hands-on experience in ASIC STA and timing closure.
• Expert proficiency in industry-standard sign-off tools from Cadence or Synopsys.
• Advanced knowledge of OCV, signal integrity, and IR-drop aware STA.
• Strong expertise in Tcl, Python, and other shell scripting languages.
• Must be legally authorized to work in the United States.

Culture & Benefits

• Comprehensive medical, dental, and vision insurance plans.
• 401(k) participation with company matching.
• Employee Stock Purchase Program (ESPP) and equity awards.
• Paid time off, including holidays, sick leave, and vacation.
• Discretionary annual bonus eligibility based on performance.
• Equal opportunity employer committed to a diverse workforce.