Physical IC Design Engineer (AI)

TL;DR

Physical IC Design Engineer (AI): Executing all physical design aspects of taking RTL to silicon tape-out for AI/ML ecosystems and enterprise storage products with an accent on synthesis, physical verification, and timing closure. Focus on place and route, clock tree synthesis, and flow methodology development to ensure world-class chip performance.

Location: Must work in person at our San Jose, CA site: no remote work allowed.

Salary: $120,000 - $192,000

Company

hirify.global is a global technology leader that designs, develops, and supplies a broad range of semiconductor and infrastructure software solutions.

What you will do

• Execute physical design, synthesis, physical verification, and timing closure.
• Perform setup and synthesis of RTL designs.
• Carry out EM/IR analysis, place and route, and clock tree synthesis.
• Develop floor-planning and layout strategies.
• Collaborate with IC design RTL engineers on complex silicon tape-outs.
• Develop and improve physical design flows and methodologies.

Requirements

• Minimum of 8 years of relevant experience.
• Bachelor’s degree in Electrical or Electronics Engineering.
• Must work onsite at our San Jose, CA location.
• Proficiency in TCL/PERL scripting and related EDA tools.
• Proven experience in the full physical design cycle from RTL to tape-out.
• Excellent verbal and written communication skills.

Culture & Benefits

• Comprehensive medical, dental, and vision insurance plans.
• 401(k) participation with company matching.
• Employee Stock Purchase Program (ESPP) and discretionary annual bonuses.
• Paid holidays, sick leave, and vacation time.
• Commitment to an inclusive work environment with equal opportunity employment practices.