Senior ASIC Design Engineer (AI)

TL;DR

Senior ASIC Design Engineer (AI): Designing and implementing complex RTL logic for AI/HPC SOCs in the custom silicon business unit of a Tier 1 semiconductor company with an accent on synthesis, timing closure, and system-level architecture. Focus on developing synthesis constraints, performing lab bring-up, and integrating high-performance processor sub-systems.

Location: Headquartered in Ottawa, Canada (searching globally)

Salary: $140,000 - $190,000 plus bonus

Company

hirify.global is a Canadian firm specializing in ASIC and FPGA design, verification, and embedded software development services.

What you will do

• Translate system-level requirements into detailed, implementable architecture and design specifications.
• Design and implement complex RTL logic primarily using Verilog or System Verilog.
• Develop synthesis and timing constraints for complex blocks and sub-systems.
• Perform block-level simulation, ASIC synthesis, and timing closure.
• Execute lab bring-up, product integration, and system-level troubleshooting.
• Lead customers through complex technical issues and provide high-level support.

Requirements

• Minimum 5 years of relevant experience in ASIC design.
• Expertise in RTL logic design, synthesis, STA, lint, LEC, and PnR processes.
• Experience with ARM or RISC-V Application Processor Sub-Systems and Processor Fabric Interfaces.
• Knowledge of industry-standard interfaces such as PCIe, Ethernet, AXI, AMBA, or DDR/SDRAM.
• Proven track record in lab environments and troubleshooting issues up to the system level.
• Must have strong test verification and scripting experience.

Culture & Benefits

• Access to challenging, stimulating technical environments with world-leading innovation.
• Culture of trust and appreciation where every employee is engaged.
• Strong commitment to work-life balance, ensuring time for family and friends.
• Comprehensive benefits plan and company performance bonuses.