Senior DFT Engineer (AI)

TL;DR

Senior DFT Engineer (AI/Semiconductors): Designing and integrating multiple chiplets into a System-in-package for high-performance AI platforms with an accent on DFT implementation for high-speed CPU cores. Focus on building chip-level DFT strategies, automating flows, and supporting silicon bring-up and debug.

Location: Japan

Company

hirify.global is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency.

What you will do

• Develop and implement comprehensive chip-level DFT strategies.
• Insert and verify DFT features, including scan chains, memory BIST, and JTAG.
• Collaborate with RTL, physical design, and verification teams to ensure testability throughout the design flow.
• Script and automate DFT flows using industry-standard EDA tools (Cadence, Synopsys, Siemens).
• Run and analyze ATPG and fault coverage reports.
• Support silicon bring-up and debug processes related to test features.

Requirements

• Bachelor, Master or PhD degree in electrical, computer engineering, or computer science.
• At least 10 years of relevant industry experience.
• Proficiency with DFT standard tools (Synopsys/Siemens) and scripting languages (TCL, Python).
• Proven experience in DFT planning and SoC silicon debug.
• English: Excellent verbal and written communication skills are required.
• Eligibility: Must be eligible to access U.S. export-controlled technology (EAR compliance).

Nice to have

• Fluency in Japanese.
• Possession of a Japanese work visa.