Senior DFT Engineer, Architecture

Location: Tokyo, Japan

Company

Tenstorrent develops AI computing technology, including high-performance RISC-V CPUs and AI platforms spanning software, compilers, networking, platforms, and semiconductors.

What you will do

• Build chip-level DFT strategies for high-speed CPU core designs.
• Insert and verify scan chains, memory BIST, JTAG, and other test features.
• Collaborate with RTL, physical design, and verification teams to ensure testability throughout the design flow.
• Script and automate DFT flows using industry-standard EDA tools such as Cadence, Synopsys, and Siemens.
• Run and analyze ATPG and fault coverage reports, optimizing test coverage and supporting silicon bring-up and debug.
• Perform formal verification and signoff of inserted DFT logic while collaborating with experts and external stakeholders across multiple countries.

Requirements

• Bachelor’s, master’s, or PhD degree in electrical engineering, computer engineering, or computer science.
• At least 10 years of relevant industry experience.
• Professional experience with DFT standard tools, including Synopsys or Siemens, and scripting with TCL and Python.
• Experience with DFT planning, system-on-chip development, silicon debug, and test coverage optimization.
• Ability to develop DFT plans, monitor key indicators, communicate resource needs, and scope delivery risks.
• Excellent verbal and written English communication and strong cross-functional collaboration skills.

Nice to have

• Fluency in Japanese.
• Japanese work visa.

Culture & Benefits

• Work with AI and semiconductor specialists across the USA, Japan, and other countries.
• Collaborative environment focused on curiosity, solving complex problems, and building high-performance AI platforms.
• Opportunity to contribute to a high-profile chiplet and system-in-package project with external stakeholders.