Principal SoC Architect (ML Accelerators)

TL;DR

Principal SoC Architect (ML Accelerators): Defining architectures and design tradeoffs of ML-centric SoCs that fuse analog precision, digital signal processing, and embedded machine learning with an accent on custom accelerators, memory hierarchies, and SoC fabrics. Focus on prototyping breakthrough architectures, validating them in real-world scenarios, and charting the path to scalable silicon implementation.

Location: Austin, Texas. Must be able to access technical data without a requirement for an export license. We are unable to sponsor or obtain export licenses for this role.

Company

hirify.global is propelled by top engineers in mixed-signal processing, solving complex challenges with innovative end-user solutions for the world's top consumer brands.

What you will do

• Define the end-to-end architecture for ML accelerators and SoCs, including compute fabrics, dataflows, and memory hierarchies.
• Translate domain-specific requirements into architectural specifications and accelerator designs.
• Lead architectural exploration of performance, power, area, and cost tradeoffs.
• Collaborate at the instruction set and compiler/toolchain level to co-optimize for ML workloads and domain-specific kernels.
• Partner with internal engineering, startups, and research institutions to rapidly prototype candidate architectures.
• Define and evaluate on-chip security architectures, ensuring robust protection for ML-enabled SoCs.

Requirements

• Ph.D or Master’s degree in Electrical Engineering, Computer Engineering, or related technical field.
• 10+ years in SoC or accelerator design, with a focus on ML, DSP, or high-performance edge compute.
• Deep understanding of ML accelerator architectures, including systolic arrays, SIMD/VLIW, RISC-V/ARM integration, memory subsystems, and dataflow optimization.
• Hands-on experience defining ISAs or ISA extensions and collaborating with compiler/runtime teams.
• Familiarity with the architectural implications of coupling ML compute with analog/mixed-signal front ends.
• Strong experience in architectural modeling, workload benchmarking, and system-level tradeoff analysis.

Nice to have

• Experience in hardware-level security stacks, including TEEs, enclaves, memory isolation schemes, secure boot, and cryptographic accelerators.
• Experience driving early-stage architectural concepts from exploration through to prototype.
• Expertise in energy-efficient architectures for edge workloads.

Culture & Benefits

• Award-winning culture built on a foundation of inclusion and fairness.
• Meaningful community engagement.
• Enjoyable employee experiences.