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14 часов назад

Platform Integration Engineer

164 470 - 269 100$
Формат работы
hybrid
Тип работы
fulltime
Грейд
middle
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify RU Global, списка компаний с восточно-европейскими корнями
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Описание вакансии

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TL;DR

Platform Integration Engineer: Designing and developing high-performance networks-on-chip for multiple SoCs within hirify.global with an accent on SoC chassis requirements and meeting PPA requirements. Focus on coordinating with the foundation IP development team to modify/create IP components as per SoC needs.

Location: US, California, Santa Clara; US, Oregon, Hillsboro; US, California, Folsom; US, Texas, Austin. This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned hirify.global site and off-site.

Salary: $164,470.00-269,100.00 USD

Company

hirify.global's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies).

What you will do

  • Work with the SoC architecture teams to understand the SoC chassis requirements.
  • Design and develop high-performance networks-on-chip which meet the SoC PPA requirements.
  • Coordinate with the foundation IP development team within the Chassis Group to modify/create IP components as per SoC needs.

Requirements

  • Bachelor's in Science, Electrical Engineering or equivalent with 5+ years experience – OR – Master's degree in Science, Electrical Engineering or equivalent with 4+ years experience.
  • Experience in SOC and/or IP design.
  • Experience in SoC interconnect design and microarchitecture, coherent and non-coherent fabrics, AMBA/PCIe/CXL protocols and memory subsystems.

Nice to have

  • 8+ years of experience in: SOC and/or IP design.
  • Microarchitecture and design of IP sub-systems including 5+ years' experience in fabrics for AI SoCs.
  • Expertise in Verilog/System Verilog, Lint/CDC/RDC.
  • Expertise in AMBA protocols (CHI, AXI, AHB, APB) and PCIe/CXL.
  • Experience in designing credit-based interconnect systems with QoS, security, debug/trace and RAS.

Culture & Benefits

  • We offer a total compensation package that ranks among the best in the industry.
  • It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation.

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