Staff DFT Engineer

TL;DR

Staff DFT Engineer: Implementing and verifying scan-based DFT, including Scan Streaming Network (SSN) and IJTAG (IEEE 1687), with an accent on end-to-end scan execution from insertion and verification through DRC closure, coverage improvement, and final DFT signoff. Focus on scan quality, coverage closure, and DFT signoff for complex SoC designs.

Location: Santa Clara, CA

Salary: 128,000 - 189,370 USD per annum

Company

hirify.global’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world.

What you will do

• Lead hands-on scan DFT implementation, including scan insertion, stitching, Scan Streaming Network (SSN) implementation, and IJTAG (IEEE 1687) insertion and connectivity.
• Perform scan DFT verification, debug, and DFT DRC closure.
• Debug and resolve scan-related DRCs, connectivity issues, and control signal problems.
• Generate, simulate, and debug ATPG scan patterns, analyze ATPG results, and drive scan coverage improvement and closure.
• Develop and validate DFT-related timing constraints and optimize scan implementations for pattern efficiency and test quality.
• Collaborate closely with RTL and Physical Design teams to resolve scan-related issues and support pre-silicon DFT signoff and post-silicon pattern bring-up and debug.

Requirements

• Bachelor’s degree in Computer Science, Electrical Engineering, or related fields and 5-10 years of related professional experience OR Master’s degree and/or PhD in Computer Science, Electrical Engineering, or related fields with 3-5 years of experience.
• 8+ years of hands-on experience in DFT scan implementation.
• Strong expertise with Siemens Tessent, including scan insertion and verification, ATPG pattern generation and coverage analysis, and IJTAG (IEEE 1687) and SSN implementation.
• Strong understanding of Scan Streaming Network (SSN) and IEEE 1149.x, IEEE 1500, and IEEE 1687 standards.
• Proven ability to resolve scan DFT DRCs and drive coverage closure.
• Strong TCL scripting skills for automation and flow customization and full DFT lifecycle experience, from RTL/netlist through silicon debug.

Nice to have

• Experience with scan compression and advanced scan architectures.
• Post-silicon experience, including pattern bring-up and debug, silicon characterization, and yield learning.
• Experience mentoring junior engineers or owning DFT scan signoff.

Culture & Benefits

• Employee stock purchase plan with a 2-year look back.
• Family support programs to help balance work and home life.
• Robust mental health resources to prioritize emotional well-being.
• Recognition and service awards to celebrate contributions and milestones.