Principal Verification Engineer

TL;DR

Principal Verification Engineer: Verifying circuitry for high-speed data transfer chips with an accent on test plan development, execution, debugging, and coverage closure. Focus on root-cause analysis of simulation failures and collaborating with logic designers for successful project outcomes.

Location: Santa Clara, CA

Salary: $158,600 - $237,600 per annum

Company

hirify.global’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world.

What you will do

• Architect and implement simulation test bench in UVM.
• Develop and execute test-plans for verifying correctness and performance of the design.
• Own and debug failures in simulation to root-cause problems.
• Collaborate closely with logic designers for test plan development, execution, debug, coverage closure, and gate level simulations.
• Coach and mentor junior engineers to achieve successful project outcomes.

Requirements

• Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 7+ years of related professional experience. Or Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 4+ years of experience.
• Strong background in SOC verification and test bench development using UVM, System Verilog, C/C++, and DPI.
• Strong verification skills, understanding of methodology (object-oriented programming, white-box/black-box, directed/random testing, coverage, gate-level simulations, data structure).
• Must have effective interpersonal and teamwork skills.
• Must have the ability to define problems, issues and opportunities, analyze data, establish facts, and draw valid conclusions from various datasets.

Culture & Benefits

• Employee stock purchase plan with a 2-year look back.
• Family support programs to help balance work and home life.
• Robust mental health resources to prioritize emotional well-being.
• Recognition and service awards to celebrate contributions and milestones.