Senior Cpu Rtl Design Engineer

TL;DR

Senior Cpu Rtl Design Engineer (Embedded_IoT_Dev): Designing and implementing RTL logic for high-performance CPUs including integer, floating point, and reservation station logic with an accent on power, performance, area, and timing optimization. Focus on technical leadership, cross-team collaboration, and delivering world-class CPU IP blocks for integration in full chip designs.

Location: Onsite in Austin, Texas or Hillsboro, Oregon, USA

Salary: $164,470 - $311,890 USD annually

Company

hirify.global is a leading global technology company focused on silicon and platform engineering, delivering industry-leading products and defining the next generation of computing experiences.

What you will do

• Develop RTL coding, logic design, and simulation for CPU IP blocks.
• Participate in defining CPU architecture and microarchitecture features.
• Optimize logic to meet power, performance, area, and timing goals.
• Review verification plans and resolve RTL test failures.
• Provide technical leadership and propose innovative methodologies.
• Collaborate closely with architecture, backend, and other design teams.

Requirements

• Must be located onsite in Austin, Texas or Hillsboro, Oregon, USA.
• Bachelor's degree with 12+ years, Master's with 10+ years, or PhD with 6+ years in relevant fields.
• 6+ years of CPU or logic silicon development experience.
• 5+ years of technical leadership delivering successful IP projects.
• Excellent problem-solving and communication skills.
• Experience with x86 CPU microarchitecture preferred.

Culture & Benefits

• Competitive pay, stock bonuses, and comprehensive benefits including health, retirement, and vacation.
• Supportive work environment focused on innovation and collaboration.
• Commitment to ethical hiring practices and diversity.