Senior Physical Verification Engineer (ASIC)

TL;DR

Senior Physical Verification Engineer (ASIC): Involved in sign-off flows, including physical verification, ESD checking, and package RDL routing with an accent on full-chip physical verification (LVS/DRC/ANT/ERC) and debugging rule decks. Focus on understanding and debugging complex rule decks, performing block-level place & route, and utilizing advanced tools like Calibre and Cadence Innovus.

Location: Onsite in San Jose, California, USA. Must be authorized to work in the US.

Salary: $141,300–$226,000

Company

hirify.global is a global technology leader designing, developing, and supplying a broad range of semiconductor and infrastructure software solutions.

What you will do

• Participate in sign-off flows for ASIC implementation.
• Perform physical verification, ESD checking, and package RDL routing.

Requirements

• Bachelors with 12+ years or Masters with 10+ years of related experience.
• Strong background in full-chip physical verification (LVS/DRC/ANT/ERC).
• Proficiency in scripting (Perl, Tcl, csh).
• Ability to understand and debug rule decks.
• Experience with block-level place & route.
• Familiarity with tools like Calibre, Redhawk & Totem, Cadence Virtuoso, Innovus, and Synopsys ICC2.

Culture & Benefits

• Competitive and comprehensive benefits package including medical, dental, and vision plans.
• 401(K) participation with company matching.
• Employee Stock Purchase Program (ESPP) and Employee Assistance Program (EAP).
• Company paid holidays, paid sick leave, and vacation time.
• Equal opportunity employer committed to diversity and inclusion.