Principal Analog/Mixed Signal CAD Engineer

TL;DR

Principal Analog/Mixed Signal CAD Engineer (Embedded_IoT_Dev): Develop and maintain advanced analog/mixed-signal CAD design automation infrastructure supporting cutting-edge FinFET and BiCMOS semiconductor technologies. With an accent on analog/mixed-signal simulation environments, EDA tool integration, and automation frameworks. Focus on architecting complex AMS design flows, improving simulation accuracy, and collaborating with cross-functional teams including foundry and photonics engineers.

Location: Onsite in Santa Clara, CA, USA

Salary: $150,680 - $225,700 per annum

Company

hirify.global is a leading semiconductor company providing essential data infrastructure solutions across enterprise, cloud, AI, and carrier architectures.

What you will do

• Architect, deploy, and maintain analog/mixed-signal simulation environments for advanced CMOS FinFET and BiCMOS technologies.
• Develop and support next-generation automated AMS design flows used company-wide.
• Collaborate with analog designers, EDA vendors, foundry, and TCAD teams to resolve complex simulation and design challenges.
• Evaluate and benchmark new EDA tools and methodologies to enhance design productivity and simulation performance.
• Define and implement custom circuit verification checks and model QA flows.
• Develop automation and productivity tools using scripting languages to streamline workflows.

Requirements

• Must be located onsite in Santa Clara, CA, USA; remote or hybrid work is not available.
• BSEE with 10–15 years or MS/PhD with 5–10 years of relevant experience in analog/mixed-signal design flows for advanced FinFET technologies.
• Proven experience with AMS simulation tools such as Cadence ADE, AMS Designer, Spectre, Synopsys PrimeSim, or equivalent.
• Strong understanding of analog/mixed-signal design flows including schematic capture, simulation, parasitic extraction, and post-layout verification.
• Experience debugging complex AMS simulation and modeling issues and collaborating cross-functionally.
• Excellent communication skills.

Nice to have

• Experience with Cadence Virtuoso Schematic Editor including PDK integration and CDF customization.
• Knowledge of advanced circuit modeling techniques.
• Programming or scripting skills in Python, TCL, Perl, and SKILL.
• Experience developing custom CAD automation or verification frameworks.
• Familiarity with silicon photonics design flows.

Culture & Benefits

• Work on cutting-edge semiconductor technology in Silicon Valley’s innovation hub.
• High technical impact across multiple product lines and global engineering teams.
• Collaborate with world-class designers, modeling experts, and EDA innovators.
• Leadership opportunities influencing CAD strategy and infrastructure company-wide.
• Comprehensive benefits supporting financial well-being, family support, mental and physical health, and recognition programs.

Hiring process

• Interviews designed to evaluate individual experience, thought process, and communication skills in real time.
• Use of AI tools during interviews is prohibited and may result in disqualification.
• Applicants may be subject to export license review prior to employment due to U.S. export control laws.