RTL IC Design Engineer

TL;DR

Senior RTL IC Design Engineer: Building and optimizing digital IC designs for AI/ML ecosystems and PCIe Switch Products with an accent on Verilog/SystemVerilog RTL implementation, timing closure, and debugging. Focus on developing micro-architecture, integrating third-party IP, and supporting cross-functional teams in validation.

Location: Must work in person at our Colorado Springs site: no remote work allowed.

Salary: $108,000–$172,800 annually

Company

hirify.global is a global technology leader that designs, develops and supplies a broad range of semiconductor and infrastructure software solutions.

What you will do

• Analyze high-level architecture specifications and develop micro-architecture.
• Implement high-quality, high-performance Verilog/SystemVerilog RTL designs.
• Optimize RTL for timing closure and debug RTL solutions.
• Work with cross-functional teams (Verification, Software/Firmware, Emulation, Validation Engineering).
• Provide lab support for silicon validation.

Requirements

• Bachelor’s degree in Electrical Engineering, Electronics Engineering, Computer Science, Computer Engineering, or equivalent.
• 8+ years of relevant industry experience.
• In-depth knowledge of RTL design and implementation using Verilog/SystemVerilog.
• Strong RTL debugging skills.
• Must work in person at our Colorado Springs site; no remote work allowed.

Nice to have

• Experience with PCIe protocol.
• Knowledge of CXL or AMBA protocols.
• Familiarity with RAID Storage or PCIe Switch designs.

Culture & Benefits

• Competitive and comprehensive benefits package.
• Medical, dental, and vision plans.
• 401(K) participation including company matching.
• Employee Stock Purchase Program (ESPP) and Employee Assistance Program (EAP).
• Company paid holidays, paid sick leave, and vacation time.